The present disclosure relates to a memory system making use of a non-volatile memory and relates to an operation method of such a memory system.
In the past, there has been used a memory system (also referred to as a storage system) which reads out programs, data and the like from a memory functioning as a storage device (also referred to as an auxiliary storage apparatus) into a work memory (also referred to as a main storage apparatus) implemented by typically a DRAM (Dynamic Random Access Memory) in an operation called a loading operation. In this memory system, an NVM (Non-Volatile Memory) is generally used to serve as the storage device which is required to operate at a high speed.
The non-volatile memory can be a flash memory or an NVRAM (Non-Volatile Random Access Memory). The flash memory has a large storage capacity. Data stored in the flash memory is accessed in block units. On the other hand, high-speed random accesses can be made to data stored in the NVRAM in word units. A representative example of the flash memory is a NAND-type flash memory. On the other hand, representative examples of the NVRAM are a PCRAM (Phase-Change Random Access Memory), an MRAM (Magnetoresistive Random Access Memory) and a ReRAM (Resistance Random Access Memory).
Since the flash memory has a low bit cost and a large storage capacity, the flash memory is used in high-speed storage applications. On the other hand, the NVRAM has a high bit cost in comparison with the flash memory. However, the NVRAM has the following merits. The NVRAM has an excellent performance of allowing high-speed accesses to be made in word units. In addition, since a CPU (Central Processing Unit) is capable of making direct accesses to the NVRAM, the NVRAM is used as a non-volatile cache memory for the storage device in order to allow the operation of the memory system to be carried out expectedly at a high speed.
Typical examples of a memory system making use of such a flash memory and such an NVRAM are described in documents such as JP-T-2004-506256 (Patent Document 1) and Japanese Patent Laid-Open No. 2006-236304 as well as Shuhei Tanakamaru and four coauthors, “Post-manufacturing 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC scheme for Highly Reliable Solid-State Drives, SSDs,” Memory Workshop (IMW), 2010 IEEE International, p. 1-4. The memory system is also referred to as a non-volatile memory system.